Si52146
PCI-E
XPRESS
G
EN
1, G
EN
2, & G
EN
3 S
IX
O
UTPUT
C
LOCK
G
ENERATOR
Features
PCI-Express Gen 1, Gen 2, &
Gen 3 compliant
Low power push-pull type
differential output buffers
Integrated resistors on differential
clocks
Dedicated output enable pin for
each clock
Hardware selectable spread
control
Six PCI-Express clocks
25 MHz crystal input or clock
input
I
2
C support with readback
capabilities
Triangular spread spectrum
profile for maximum
electromagnetic interference
(EMI) reduction
Industrial temperature:
–40 to 85
o
C
3.3 V Power supply
32-pin QFN package
Ordering Information:
See page 18
Applications
Network attached storage
Multi-function printer
Pin Assignments
CKPWRGD_PDB
1
SDATA
26
XOUT
OE1
1
OE0
1
32
31
30
29
VDD
XIN
28
27
25
24 VDD
23 DIFF5
22 DIFF5
21 VDD
Description
The Si52146 is a spread-controlled PCIe clock generator that can source
six PCIe clocks simultaneously. The device has six hardware inputs for
enabling the respective outputs on the fly while powered on along with the
spread control hardware pin to enable Spread for EMI reduction.
VDD
OE2
1
SSON
2
OE3
1
OE4
1
OE5
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
GND
SCLK
20
Wireless access point
Routers
DIFF4
19 DIFF4
18
DIFF3
NC
VDD
17 DIFF3
DIFF1
DIFF0
DIFF0
DIFF1
DIFF2
VDD
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
DIFF0
XIN/CLKIN
XOUT
DIFF1
Patents pending
PLL1
(SSC)
Divider
DIFF2
DIFF3
DIFF4
SCLK
SDATA
CKPWRGD/PDB
OE [5:0]
SSON
DIFF5
Control & Memory
Control
RAM
Preliminary Rev. 0.1 12/11
Copyright © 2011 by Silicon Laboratories
DIFF2
VDD
Functional Block Diagram
Si52146
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
