Si52147
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Load Capacitance (each side)
Ce
= 2 x CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
(
Ce1 + Cs1 + Ci1
+
1
1
Ce2 + Cs2 + Ci2
)
Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
CL:
2.2. CKPWRGD_PDB (Power down) Clarification
The CKPWRGD_PDB pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Upon the
first powerup if the CKPWRGD is low, the device outputs will be disabled, but the crystal oscillator and I
2
C logics
are active. Once CKPWRGD has been sampled high by the clock chip, the pin assumes a PDB functionality. When
the pin has assumed a PDB functionality and the pin is pull low, the device will be placed in standby mode.
2.3. PDB (Power down) Assertion
The PDB pin is an asynchronous active low input used to disable all clocks in a glitch free manner. All outputs will
be driven low in power down mode. In power down mode, all outputs, the crystal oscillator and the I
2
C logic are
disabled.
2.4. PDB Deassertion
When a valid rising edge on CKPWRGD/PDB pin is applied, all outputs are enabled in a glitch free manner within
two to six output clock cycle.
2.5. OE Clarification
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE
pin needs to be logic high and the I
2
C output enable bit needs to be logic high. There are two methods to disable
the output clocks: the OE is pulled to a logic low, or the I
2
C enable bit is set to a logic low. The OE pins is required
to be driven at all time and even though it has an internally 100 k resistor.
2.6. OE Assertion
The OE signals are active high input used for synchronous stopping and starting the DIFF output clocks respectively
while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high
causes stopped respective DIFF output to resume normal operation. No short or stretched clock pulses are produced
when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output
clock cycles.
2.7. OE Deassertion
When the OE pin is deasserted by making its logic low, the corresponding DIFF output is stopped cleanly, and the
final output state is driven low.
2.8. SSON Clarification
SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is
enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread.
8
Preliminary Rev. 0.1
SILABS [ SILICON LABORATORIES ]
