Si52147
4. Control Registers
4.1. Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through
the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled
or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up.
The use of this interface is optional. Clock device register changes are normally made at system initialization, if any
are required. The interface cannot be used during system operation for power management functions.
4.2. Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most
significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read
operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded
in the command code described in Table 1 on page 4.
The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Table 5. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
8:2
9
Slave address—7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code—8 bits
Acknowledge from slave
Byte Count—8 bits
Acknowledge from slave
Data byte 1–8 bits
10
Acknowledge from slave
18:11
19
18:11 Command Code–8 bits
19
20
Acknowledge from slave
Repeat start
27:20
28
27:21 Slave address–7 bits
36:29
37
28
29
Read = 1
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
45:38
46
37:30 Byte Count from slave–8 bits
38 Acknowledge
46:39 Data byte 1 from slave–8 bits
47 Acknowledge
55:48 Data byte 2 from slave–8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
....
....
....
....
56
....
....
....
....
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Preliminary Rev. 0.1
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SILICON [ SILICON ]
