Si52142
PCI-E
XPRESS
G
EN
1, G
EN
2 & G
EN
3 C
L O C K
T
W O
O
UTPUT
G
EN ERATOR WITH
25 MH
Z
R
EFERENCE
C
L O C K
Features
PCI-Express Gen 1, Gen 2 &
Gen 3 compliant
Low power push-pull type
differential output buffers
Integrated resistors on differential
clocks
Dedicated output enable
hardware pin for each clock
Hardware selectable spread
control
Two PCI-Express clocks
25 MHz reference clock
25 MHz crystal input or clock
input
I
2
C support with readback
capabilities
Triangular spread spectrum
profile for maximum
electromagnetic interference
(EMI) reduction
Industrial temperature
–40 to 85
o
C
3.3 V power supply
24-pin QFN package
Ordering Information:
See page 18
Applications
Network attached storage
Multi-function printer
Pin Assignments
VDD_CORE
VSS_CORE
XIN/CLKIN
SDATA
20
Description
The Si52142 is a spread-controlled PCIe clock generator that can source
two PCIe clocks and a 25 MHz reference clock. The device has three
hardware output enable control inputs for enabling the respective outputs
on the fly while powered on along with the hardware input for spread
spectrum and frequency control on outputs. In addition to the hardware
control pins, I
2
C programmability is also available to promptly achieve
optimum clock signal integrity through skew and edge rate control on true,
compliment, or both differential outputs as well as amplitude control.
24
VDD_REF
REF
OE_REF
1
VSS_REF
OE_DIFF0
1
VDD_DIFF
1
2
3
4
5
6
7
23
22
XOUT
21
SCLK
19
1
18 OE_DIFF1
Wireless access point
Routers
17 VDD_DIFF
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
8
2
25
GND
9
10
11
12
NC
NC
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Functional Block Diagram
Patents pending
XIN/CLKIN
XOUT
REF
DIFF0
PLL1
(SSC)
Divider
DIFF1
SCLK
SDATA
OE_REF
OE [1:0]
SS [1:0]
Control & Memory
Control
RAM
Preliminary 0.1 12/11
Copyright © 2011 by Silicon Laboratories
VDD_DIFF
SS0
2
SS1
NC
Si52142
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.