Si5323
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Description
The Si5323 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging
from 8 kHz to 707 MHz and generates two equal
frequency-multiplied clock outputs ranging from 8 kHz
to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5323 is based on Silicon Laboratories' 3rd-
generation DSPLL
®
technology, which provides any-
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5323 is ideal for providing clock
multiplication and jitter attenuation in high performance
timing applications.
Features
Selectable output frequencies ranging from 8 kHz to
1050 MHz
Ultra-low jitter clock outputs with jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs w/manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOL, LOS alarm outputs
Pin-controlled output phase adjust
Pin-programmable settings
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 line cards
Optical modules
Test and measurement
Xtal or Refclock
CKIN1
CKOUT1
DSPLL
CKIN2
®
Signal Format
CKOUT2
Disable/BYPASS
Loss of Signal
Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select
Bandwidth Select
Rate Select
Manual/Auto Switch
/
Clock Select
Latency Control
Preliminary Rev. 0.2 3/07
Copyright © 2007 by Silicon Laboratories
Si5323
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
