Si5325
2. Pin Descriptions: Si5325
CLKOUT1–
CLKOUT2+
CMODE
CLKOUT2–
CLKOUT1+
27 SDI
26 A2_SS
25 A1
24 A0
23 SDA_SDO
22 SCL
21 CS_CA
20 NC
19 NC
10 11 12 13 14 15 16 17 18
CLKIN2+
CLKIN1+
VDD
VDD
NC
CLKIN2–
VDD
CLKIN1–
NC
VDD
GND
NC
36 35 34 33 32 31 30 29 28
RST
NC
INT_C1B
C2B
1
2
3
4
VDD 5
GND
NC
GND
6
7
8
GND
Pad
NC 9
Pin numbers are preliminary and subject to change.
Pin #
1
Pin Name
RST
I/O
I
Signal Level
LVCMOS
Table 3. Si5325 Pin Descriptions
Description
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces
the device registers to their default value. Clock outputs are
tristated during reset. After rising edge of RST signal, the
Si5325 will perform an internal self-calibration.
This pin has a weak pull-up.
No Connect.
This pin must be left unconnected for normal operation.
Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm
output for CKIN1. If used as an interrupt output,
INT_PIN
must be set to 1. The pin functions as a maskable interrupt
output with active polarity controlled by the
INT_POL
register
bit.
If used as an alarm output, the pin functions as a LOS (and
optionally FOS) alarm indicator for CKIN1. Set
CK1_BAD_PIN
= 1 and
INT_PIN
= 0.
0 = CKIN1 present.
1 = LOS (FOS) on CKIN1.
The active polarity is controlled by
CK_BAD_POL.
If no func-
tion is selected, the pin tristates.
2, 7, 9, 14,
18, 19, 20,
30, 33
3
NC
—
—
INT_C1B
O
LVCMOS
Note:
Internal register names are indicated by underlined italics, e.g.
INT_PIN.
See Si5325 Register Map.
6
Preliminary Rev. 0.26
NC
SILABS [ SILICON LABORATORIES ]
