Si5317
P
R E L I M I N A R Y
D
A TA
S
H E E T
P
I N
- C
ONTR OLLED
1–710 MH
Z
J
I T T E R
C
LEAN ING
C
LOCK
Features
Provides jitter attenuation on any
frequency
One clock input / two clock outputs
Input/output frequency range:
1–710 MHz
Ultra low jitter: 300 fs
(12 kHz–20 MHz) typical
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 Hz–8.4 kHz
Selectable output clock signal
format: LVPECL, LVDS, CML or
CMOS
Single supply: 1.8, 2.5, or 3.3 V
VCO freeze during LOS/LOL
Loss of lock and loss of signal alarms
On-chip voltage regulator with high
PSRR
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 ºC
Applications
Ordering Information:
Data converter clocking
Wireless infrastructure
Networking, SONET/SDH
Switches and routers
Medical instrumentation
Test and measurement
See page 43.
Description
The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications
that require jitter attenuation without clock multiplication. The Si5317 accepts a
single clock input ranging from 1 to 710 MHz and generates two low jitter clock
outputs at the same frequency. The clock frequency range and loop bandwidth are
selectable from a simple look-up table. The Si5317 is based on Silicon
Laboratories' 3rd-generation DSPLL
®
technology, which provides jitter attenuation
on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is user
selectable, providing jitter performance optimization at the application level.
Pin Assignments
CKOUT1–
CKOUT2+
CKOUT2-
SFOUT0
CKOUT1+
27 FRQSEL3
26 FRQSEL2
25 FRQSEL1
24 FRQSEL0
23 BWSEL1
22 BWSEL0
21 NC
20 DEC
19 INC
10 11 12 13 14 15 16 17 18
CKIN+
VDD
NC
NC
CKIN–
RATE0
DBL2_BY
RATE1
LOL
SFOUT1
VDD
36 35 34 33 32 31 30 29 28
RST 1
FRQTBL 2
LOS 3
NC 4
VDD 5
XA 6
XB
7
NC
GND
Pad
Functional Block Diagram
XTAL/Clock
GND 8
NC 9
Clock Out1
Clock In
DSPLL
®
Signal Format [1:0]
Clock Out2
Status/Control
High
PSRR
Regulator
VDD (1.8, 2.5, 3.3 V)
GND
Frequency Table
Frequency Select [3:0]
Bandwidth Select [1:0]
Phase Skew INC/DEC
Loss of Lock
Loss of Signal
XTAL/Clock Rate [1:0]
Preliminary Rev. 0.15 4/10
Copyright © 2010 by Silicon Laboratories
GND
Si5317
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
