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SI532 参数 Datasheet PDF下载

SI532图片预览
型号: SI532
PDF下载: 下载PDF文件 查看货源
内容描述: 双频XO ( 10 MHz至1.4 GHz)的 [DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ)]
分类和应用: 石英晶振
文件页数/大小: 10 页 / 174 K
品牌: SILABS [ SILICON LABORATORIES ]
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Si532
P
R E L I M I N A R Y
D
A TA
S
H E E T
D
UAL
F
REQUENCY
XO (10 MH
Z
Features
Available with any-rate output
frequencies from 10 to 945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
Industry standard 7x5 mm package
Available CMOS, LVPECL, LVDS &
CML outputs
3.3, 2.5, and 1.8 V supply options
TO
1 . 4 GH
Z
)
3x better frequency stability than
SAW based oscillators
3rd generation DSPLL
®
with
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Lead-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low jitter clock generation
Optical modules
Test and measurement
Ordering Information:
See page 7.
Description
The Si532 dual frequency XO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si532 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional XOs where a
different crystal is required for each output frequency, the Si532 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to be optimized for superior
frequency, stability, and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments often found in communication
systems. The Si532 IC based XO is factory configurable for a wide variety of
user specifications including frequency, supply voltage, and output format.
Specific configurations are factory programmed into the Si532 at the time of
shipment, thereby eliminating the long lead times associated with custom
oscillators.
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
FS
OE
GND
Preliminary Rev. 0.3 12/05
Copyright © 2005 by Silicon Laboratories
Si532
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.