Si5367
P
R E L I M I N A R Y
D
A TA
S
H E E T
µP-P
R O G R A M M A B L E
P
R E C I S I O N
C
L O C K
M
U L T I P L I E R
Description
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs ranging
from 10 to 707 MHz and generates five frequency-multiplied
clock outputs ranging from 10 to 945 MHz and select
frequencies to 1.4 GHz. The device provides virtually any
frequency translation combination across this operating
range. The outputs are divided down separately from a
common source. The Si5367 input clock frequency and clock
multiplication ratio are programmable through an I
2
C or SPI
interface. The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL
®
technology, which provides any-rate
frequency synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter
components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at
the application level. Operating from a single 1.8 or 2.5 V
supply, the Si5367 is ideal for providing clock multiplication in
high performance timing applications.
Features
Generates any frequency from 10 to 945 MHz and
select frequencies to 1.4 GHz from an input
frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(30 kHz to 1.3 MHz)
Four clock inputs w/manual or automatically
controlled hitless switching
Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOS alarm outputs
Digitally-controlled output phase adjust
I
2
C or SPI programmable settings
On-chip voltage regulator for 1.8 or 2.5 V ±10%
operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
CKIN1
CKIN2
CKIN3
CKIN4
÷ N31
÷ N32
÷ N33
÷ N34
÷ N2
÷ NC3
CKOUT3
÷ NC1
CKOUT1
DSPLL
®
÷ NC2
CKOUT2
÷ NC4
I
2
C/SPI Port
Clock Select
Device Interrupt
LOS Alarms
Control
÷ NC5
CKOUT4
CKOUT5
VDD (1.8 or 2.5 V)
GND
Preliminary Rev. 0.3 3/07
Copyright © 2007 by Silicon Laboratories
Si5367
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
