Si823x
Table 1. Electrical Characteristics
1
(Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
VDDA, VDDB Undervoltage
Threshold
5 V threshold
8 V threshold
10 V threshold
12.5 V threshold
VDDA, VDDB Undervoltage
Threshold
5 V threshold
8 V threshold
10 V threshold
12.5 V threshold
VDDA, VDDB
Lockout hysteresis
VDDA, VDDB
Lockout hysteresis
VDDA, VDDB
Lockout hysteresis
AC Specifications
Symbol
VDDI
UV+
VDDI
UV–
VDDI
HYS
VDDA
UV+
,
VDDB
UV+
Test Conditions
VDDI rising
VDDI falling
Min
3.60
3.30
—
Typ
4.0
3.70
250
Max
4.45
4.15
—
Units
V
V
mV
VDDA, VDDB rising
See Figure 36 on page 25.
See Figure 37 on page 25.
See Figure 38 on page 25.
See Figure 39 on page 25.
5.20
7.50
9.60
12.4
5.80
8.60
11.1
13.8
6.30
9.40
12.2
14.8
V
V
V
V
VDDA
UV–
,
VDDB
UV–
VDDA, VDDB falling
See Figure 36 on page 25.
See Figure 37 on page 25.
See Figure 38 on page 25.
See Figure 39 on page 25.
4.90
7.20
9.40
11.6
—
—
—
5.52
8.10
10.1
12.8
280
600
1000
6.0
8.70
10.9
13.8
—
—
—
V
V
V
V
mV
mV
mV
VDDA
HYS
,
VDDB
HYS
VDDA
HYS
,
VDDB
HYS
VDDA
HYS
,
VDDB
HYS
UVLO voltage = 5 V
UVLO voltage = 8 V
UVLO voltage = 10 V or 12.5 V
Minimum Pulse Width
Propagation Delay
t
PHL
, t
PLH
CL = 200 pF
—
—
10
30
—
60
ns
ns
Pulse Width Distortion
|t
PLH
- t
PHL
|
Minimum Overlap Time
Programmed Dead Time
PWD
TDD
DT
t
R
,t
F
C
L
= 200 pF (Si8230/1/2)
C
L
= 200 pF (Si8233/4/5/6)
DT = VDDI, No-Connect
—
—
—
—
—
—
—
0.4
900
70
—
—
5.60
—
—
—
12
20
ns
ns
ns
ns
ns
ns
Output Rise and Fall Time
Notes:
1.
VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2.
TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3.
The largest RDT resistor that can be used is 220 k.
Rev. 0.3
7
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