Si8430/31/35
Table 5. Electrical Characteristics
1
(Continued)
(V
DD1
= 2.70 V, V
DD2
= 2.70 V, T
A
= –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Si843xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
PLH
- t
PHL
|
Propagation Delay Skew
3
Channel-Channel Skew
All Models
Output Rise Time
Output Fall Time
Common Mode Transient
Immunity
Enable to Data Valid
4
Enable to Data Tri-State
4
Start-up Time
4,5
Symbol
Test Condition
Min
Typ
Max
Unit
0
—
t
PHL
, t
PLH
PWD
t
PSK(P-P)
t
PSK
C
L
= 15 pF
See Figure 2
C
L
= 15 pF
See Figure 2
V
I
= V
DD
or 0 V
See Figure 1
See Figure 1
See Figure 2
See Figure 2
3.0
—
—
—
—
—
6.0
1.5
2.0
0.5
150
6.0
9.5
2.5
3.0
1.8
Mbps
ns
ns
ns
ns
ns
t
r
t
f
CMTI
t
en1
t
en2
t
SU
—
—
—
—
—
—
4.8
3.2
25
5.0
7.0
15
6.5
4.6
—
8.0
9.2
40
ns
ns
kV/µs
ns
ns
µs
Notes:
1.
Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to T
A
= 0 to 85 °C.
2.
The nominal output impedance of an isolator driver channel is approximately 85
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4.
See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5.
Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.5
SILABS [ SILICON LABORATORIES ]
