Si85xx
3.2.2. Selecting Reset Timing Signals
R1
Reset timing signals should be chosen to meet the
following conditions:
Satisfy reset time t
R
Not overlap integrator reset into the desired
measurement period
Not violate reset watchdog timeout period t
WD
3.2.3. Configuring Integrator Reset
Per Section “2. Functional Overview”, the integrator
must be reset (zeroed) prior to the start of each
measurement cycle to achieve specified measurement
accuracy. This reset must be synchronized with the
system switch timing signals to ensure current is
measured during the appropriate time, so the Si85xx
integrator reset circuitry uses system timing as its
reference. Timing signals connect to reset inputs R1
through R4 where built-in logic functions allow the user
to choose the conditions that cause an integrator reset
event.
Important note: reset inputs R1–R4 are rated to a
maximum input voltage of VDD. External resistor
dividers must be used when connecting driver output
signals to R1–R4 that swing beyond VDD.
R2
R3
R4
MEASURE
RESET
tR
MEASURE
RESET
tR
OUT1
OUT2
Figure 10. Full-Bridge Timing Example B
Preliminary Rev. 0.1
11
SILABS [ SILICON LABORATORIES ]
