Si5013
OC-12/3, STM-4/1 SONET/SDH CDR IC
WITH
L
IMITING
A
MPLIFIER
Features
H
igh-speed clock and data recovery device with integrated limiting amplifier:
Supports OC-12/3, STM-4/1
Loss-of-signal level alarm
Data slicing level control
DSPLL
®
technology
10 mV
PP
differential sensitivity
Jitter generation 2.3 mUI
rms
(typ)
Small footprint: 5 x 5 mm
Reference and reference-less
operation supported
3.3 V supply
Ordering Information:
See page 22.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Pin Assignments
Si5013
BER_ALM
CLKOUT+
DIN–
CLKOUT–
21 VDD
20 REXT
19 RESET/CAL
18 VDD
17 DOUT+
16 DOUT–
15 TDI
8
LTR
9
LOS
10 11 12 13 14
DSQLCH
DIN+
VDD
VDD
CLKDSBL
BER_LVL
Description
The Si5013 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-12/3 and STM-4/1 rates. Use of an external reference
clock is optional. Silicon Laboratories DSPLL
®
technology eliminates
sensitive noise entry points, thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5013 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
RATESEL
GND
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
1
2
3
4
5
6
7
28 27 26 25 24 23 22
GND
Pad
Functional Block Diagram
LOS_LVL
LOS
Signal
Detect
Retimer
DSQLCH
BUF
2
DOUT+
DOUT–
DIN+
DIN–
2
Limiting
Amp
DSPLL
BER
Monitor
BUF
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
Bias Gen.
Reset/
Calibration
BER_ALM
REXT
RATESEL
RESET/CAL
SLICE_LVL
LTR
BER_LVL
LOL
Rev. 1.6 6/08
Copyright © 2008 by Silicon Laboratories
VDD
NC
Si5013
SILABS [ SILICON LABORATORIES ]
