SiM3C1xx
Table 3.2. Power Consumption
Parameter
Digital Core Supply Current
Normal Mode
2,3,4,5
—Full speed
with code executing from Flash,
peripheral clocks ON
I
DD
F
AHB
= 80 MHz,
F
APB
= 40 MHz
F
AHB
= F
APB
= 20 MHz
F
AHB
= F
APB
= 2.5 MHz
Normal Mode
2,3,4,5
—Full speed
with code executing from Flash,
peripheral clocks OFF
I
DD
F
AHB
= 80 MHz,
F
APB
= 40 MHz
F
AHB
= F
APB
= 20 MHz
F
AHB
= F
APB
= 2.5 MHz
Power Mode 1
2,3,4,6
—Full speed
with code executing from RAM,
peripheral clocks ON
I
DD
F
AHB
= 80 MHz,
F
APB
= 40 MHz
F
AHB
= F
APB
= 20 MHz
F
AHB
= F
APB
= 2.5 MHz
Power Mode 1
2,3,4,6
—Full speed
with code executing from RAM,
peripheral clocks OFF
I
DD
F
AHB
= 80 MHz,
F
APB
= 40 MHz
F
AHB
= F
APB
= 20 MHz
F
AHB
= F
APB
= 2.5 MHz
Power Mode 2
2,3,4
—Core halted
with peripheral clocks ON
I
DD
F
AHB
= 80 MHz,
F
APB
= 40 MHz
F
AHB
= F
APB
= 20 MHz
F
AHB
= F
APB
= 2.5 MHz
Power Mode 3
2,3
I
DD
V
DD
= 1.8 V, T
A
= 25 °C
V
DD
= 3.0 V, T
A
= 25 °C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
33
10.5
2.0
22
7.8
1.2
30.5
8.5
1.7
20
5.3
1.0
19
7.8
1.3
175
250
36.5
13.3
3.8
24.9
10
3
35.5
10
3.5
23
7.3
2.8
22
9.7
3
—
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
Symbol
Conditions
Min
Typ
Max
Units
Notes:
1.
Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2.
Currents are additive. For example, where
I
DD
is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
3.
I
ncludes all peripherals that cannot have clocks gated in the Clock Control module.
4.
Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5.
Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6.
RAM execution numbers use 0 wait states for all frequencies.
7.
IDAC output current and IVC input current not included.
8.
Bias current only. Does not include dynamic current from oscillator running at speed.
Preliminary Rev. 0.8
7
SILABS [ SILICON LABORATORIES ]
