SiM3C1xx
4.4. Data Peripherals
4.4.1. 16-Channel DMA Controller
The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without
spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the
system, as the device can spend more time in low-power modes.
The DMA controller has the following features:
Utilizes
ARM PrimeCell uDMA architecture.
Implements 16 channels.
DMA crossbar supports SARADC0, SARADC1, IDAC0, IDAC1, I2C0, I2S0, SPI0, SPI1, USART0,
USART1, AES0, EPCA0, external pin triggers, and timers.
Supports primary, alternate, and scatter-gather data structures to implement various types of transfers.
Access allowed to all AHB and APB memory space.
4.4.2. 128/192/256-bit Hardware AES Encryption (AES0)
The basic AES block cipher is implemented in hardware. The integrated hardware support for Cipher Block
Chaining (CBC) and Counter (CTR) algorithms results in identical performance, memory bandwidth, and memory
footprint between the most basic Electronic Codebook (ECB) algorithm and these more complex algorithms. This
hardware accelerator translates to more core bandwidth available for other functions or a power savings for low-
power applications.
The AES module includes the following features:
Operates
on 4-word (16-byte) blocks.
Supports key sizes of 128, 192, and 256 bits for both encryption and decryption.
Generates the round key for decryption operations.
All cipher operations can be performed without any firmware intervention for a set of 4-word blocks (up to
32 kB).
Support for various chained and stream-ciphering configurations with XOR paths on both the input and
output.
Internal 4-word FIFOs to facilitate DMA operations.
Integrated key storage.
Hardware acceleration for Cipher-Block Chaining (CBC) and Counter (CTR) algorithms utilizing integrated
counterblock generation and previous-block caching.
4.4.3. 16/32-bit CRC (CRC0)
The CRC module is designed to provide hardware calculations for Flash memory verification and communications
protocols.
The CRC module supports four common polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE
802.3). The three supported 16-bit polynomials are 0x1021 (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005
(ZigBee, 802.15.4, and USB).
The CRC module includes the following features:
Support
for four common polynomials (one 32-bit and three 16-bit options).
Byte-level bit reversal for the CRC input.
Byte-order reorientation of words for the CRC input.
Word or half-word bit reversal of the CRC result.
Ability to configure and seed an operation in a single register write.
Support for single-cycle parallel (unrolled) CRC computation for 32- or 8-bit blocks.
Capability to CRC 32 bits of data per peripheral bus (APB) clock.
Support for DMA writes using firmware request mode.
Preliminary Rev. 0.8
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SILABS [ SILICON LABORATORIES ]
