SC9642
(Continued)
Pin No.
12
Pin name
RFIN
Descriptions
EFM signal input
13
RFREF
Ir
Comparator common mode input
Reference current output
Analog ground 2
14
15
VSSA2
VDDA2
16
Analog supply 2
Crystal oscillation circuit input. When the master clock is input externally, input it
from this pin.
17
CRIN
18
19
CROUT
MODE
Crystal oscillation circuit output.
Connect ground.
Control the spindle motor (during focusing and jumping, if MOT_CTRL output high
level signal, it can control the MOT control port of SA9529 after through 3 voltage
drop diodes, then prevent the spindle reverse; in other condition, the MOT-CTRL
output low level).
20
MOT_CTRL
21
22
23
24
25
26
27
28
29
30
31
WCLK_OUT
SCLK_OUT
DATA_OUT
ERR
D/A interface. LR clock output.
D/A interface. Bit clock output.
D/A interface. Serial data output
C2 error flag
WCLK_IN
SCLK_IN
DATA_IN
ACK
D/A interface. LR clock input.
D/A interface. Bit clock input.
D/A interface. Serial data input
Acknowledge Signal output pin (drain open, with pull up resistor).
DAC system clock input (16.9344MHz)
MCLK_IN
CL16
16.9344MHZ clock output
DATA \ WR
Data I/O port, it is shared with write port of parallel communication.
Control I/O port, it is shared with read port of parallel communication.(drain open,
with internal pull-up resistor).
32
STB \ RD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
ACK
Acknowledge signal port (drain open, with internal pull-up resistor).
IO.7 \ DATA7 General I/O port, it is shared with data bit 7 (drain open, with internal pull up resistor).
IO.6 \ DATA6 General I/O port, it is shared with data bit 6 (drain open, with internal pull up resistor).
IO.5 \ DATA5 General I/O port, it is shared with data bit 5 (drain open, with internal pull up resistor).
IO.4 \ DATA4 General I/O port, it is shared with data bit 4 (drain open, with internal pull up resistor).
IO.3 \ DATA3 General I/O port, it is shared with data bit 3 (drain open, with internal pull up resistor).
IO.2 \ DATA2 General I/O port, it is shared with data bit 2 (drain open, with internal pull up resistor).
IO.1 \ DATA1 General I/O port, it is shared with data bit 1 (drain open, with internal pull up resistor).
IO.0 \ DATA0 General I/O port, it is shared with data bit 0 (drain open, with internal pull up resistor).
TEST
RESET
VDDA
VSSO
VDD0
Test pin.
Reset pin (active low)
Analog Supply
Analog Ground
Analog Supply
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1
2008.03.24
Page 5 of 9
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