Preliminary
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2.1.21 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one
128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must
be 32-bit operations, i.e. 8- or 16-bit operations are not supported.
2.1.22 General Purpose Input/Output (GPIO)
In the EFM32ZG210, there are 24 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32ZG210 is a subset of the feature set described in the EFM32ZG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M0+
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
I2C0
USART0
LEUART0
TIMER0
TIMER1
RTC
PCNT0
ACMP0
VCMP
ADC0
IDAC0
AES
Configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA and I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Pin Connections
NA
DBG_SWCLK, DBG_SWDIO,
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
TIM1_CC[2:0]
NA
PCNT0_S[1:0]
ACMP0_CH[1:0], ACMP0_O
NA
ADC0_CH[3:0]
IDAC0_OUT
NA
2013-10-09 - EFM32ZG210FXX - d0065_Rev0.60
6
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