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EFM32ZG210F8-QFN32 参数 Datasheet PDF下载

EFM32ZG210F8-QFN32图片预览
型号: EFM32ZG210F8-QFN32
PDF下载: 下载PDF文件 查看货源
内容描述: 能源,煤气,水及智能电表 [Energy, gas, water and smart metering]
分类和应用:
文件页数/大小: 65 页 / 1596 K
品牌: SILICONIMAGE [ Silicon image ]
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Preliminary
...the world's most energy friendly microcontrollers
2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination
of the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time from
energy saving modes, and a wide selection of peripherals, the EFM32ZG microcontroller is well suited
for any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32ZG210 devices. For a complete feature set and in-
depth information on the modules, the reader is referred to the
EFM32ZG Reference Manual.
A block diagram of the EFM32ZG210 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
ZG210F32/ 16/ 8/ 4
Core and Mem ory
ARM Cortex ™ M0+ processor
Clock Managem ent
High Freq
Crystal
Oscillator
Low Freq
Crystal
Oscillator
High Freq
RC
Oscillator
Low Freq
RC
Oscillator
Ultra Low Freq
RC
Oscillator
Energy Managem ent
Voltage
Regulator
Brown- out
Detector
Voltage
Com parator
Power- on
Reset
Flash
Program
Mem ory
RAM
Mem ory
Debug
Interface
DMA
Controller
32- bit bus
Peripheral Ref lex Syst em
Serial Interfaces
USART
Low
Energy
Uart™
IC
2
I/ O Ports
Ex ternal
Interrupts
Pin
Reset
General
Purpose
I/ O
Pin
Wakeup
Tim ers and Triggers
Tim er/
Counter
Pulse
Counter
Real Tim e
Counter
Watchdog
Tim er
Analog Interfaces
ADC
Analog
Com parator
Security
Hardware
AES
Current
DAC
2.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 Dhrystone
MIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is in-
cluded as well. The EFM32 implementation of the Cortex-M0+ is described in detail in
ARM Cortex-M0+
Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32ZG microcontroller.
The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory is
divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2013-10-09 - EFM32ZG210FXX - d0065_Rev0.60
3
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