STK10C48
If the STK10C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
LOW AVERAGE ACTIVE POWER
The STK10C48 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK10C48 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
VCC or between E and system VCC.
HARDWARE PROTECT
The STK10C48 offers two levels of protection to
suppress inadvertent STORE cycles. If the control
signals (E, G, W and NE) remain in the STORE con-
dition at the end of a STORE cycle, a second STORE
cycle will not be started. The STORE (or RECALL)
will be initiated only after a transition on any one of
these signals to the required state. In addition to
multi-trigger protection, STOREs are inhibited when
VCC is below 4.0V, protecting against inadvertent
STOREs.
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
200
0
0
50
100
150
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
March 2006
9
Document Control # ML0002 rev 0.2
SIMTEK [ SIMTEK CORPORATION ]
