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STK10C68-5KF25M 参数 Datasheet PDF下载

STK10C68-5KF25M图片预览
型号: STK10C68-5KF25M
PDF下载: 下载PDF文件 查看货源
内容描述: 8K ×8的nvSRAM QuantumTrap⑩ CMOS非易失性静态RAM [8K x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 12 页 / 471 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK10C68
STK10C68-M SMD#5962-93056
8K x 8 nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
• 25ns, 35ns, 45ns and 55ns Access Times
STORE
to Nonvolatile Elements Initiated by
Hardware
RECALL
to SRAM Initiated by Hardware or
Power Restore
• Automatic
STORE
Timing
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments (Industrial/Commercial)
• 100-Year Data Retention (Industrial/Commer-
cial)
• Commercial, Industrial and Military Tempera-
tures
• 28-Pin DIP, SOIC and LCC Packages
DESCRIPTION
The Simtek STK10C68 is a fast static
RAM
with a nonvol-
atile element incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
Non-
volatile Elements
. Data may easily be transferred from
the
SRAM
to the
Nonvolatile Elements
(the
STORE
oper-
ation
), or from the
Nonvolatile Elements
to the
SRAM
(the
RECALL
operation), using the NE pin.
Transfers
from the Nonvolatile Elements to the
SRAM
(the
RECALL
operation) also take place automatically on
restoration of power.
The STK10C68 combines the high
performance and ease of use of a fast
SRAM
with nonvol-
atile data integrity.
The STK10C68 features industry-standard pinout for non-
volatile
RAM
s. MIL-STD-883 and Standard Military Draw-
ing (
SMD
#5962-93056) devices are available.
BLOCK DIAGRAM
QUANTUM TRAP
128 x 512
ROW DECODER
PIN CONFIGURATIONS
NE
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
128 x 512
RECALL
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - LCC
28 - DIP
28 - SOIC
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
STORE/
RECALL
CONTROL
PIN NAMES
A
0
- A
12
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Nonvolatile Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
G
NE
E
W
DQ
0
- DQ
7
E
G
NE
V
CC
V
SS
March 2006
1
Document Control # ML0006 rev 0.2