STK11C68 (SMD5962–92324)
PIN CONFIGURATIONS
1
2
3
28
NC
A12
VCC
27
26
25
W
NC
A7
A6
A5
A4
4
5
6
A8
A9
24
23
22
A11
7
A3
A2
G
8
A10
21
20
9
A1
A0
E
DQ7
10
19
18
11
12
13
DQ6
DQ5
DQ4
DQ0
DQ1
17
16
15
DQ2
VSS
14
DQ3
28-Pin LCC
28-Pin DIP
28-Pin SOIC
PIN NAMES
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
12
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, ±10%
Ground
CC
SS
Rev 0.3
Document Control #ML0007
February, 2007
2
SIMTEK [ SIMTEK CORPORATION ]
