STK12C68 (SMD5962-94599)
Packages
VCAP 1
A12 2
A7 3
A6
A5
A4
A3
A2
A1
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCCX
W
HSB
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A0 10
DQ0 11
DQ1 12
DQ2 13
VSS 14
28-pin SOIC
28-pin DIP
28-pin LCC
Pin Descriptions
Pin Name
A
12
-A
0
DQ
7
-DQ
0
E
W
G
V
CCX
HSB
Input
I/O
Input
Input
Input
Power Supply
I/O
I/O
Description
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, +10%, -10%
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
Ground
V
CAP
V
SS
Power Supply
Power Supply
Document Control #ML0008 Rev 0.7
February 2007
2
SIMTEK [ SIMTEK CORPORATION ]
