STK14D88
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
t
AXQXd
t
AVAVc
t
AVQVd
SYMBOLS
#1
#2
t
ELQV
t
ELEH
c
Alt.
t
ACS
t
RC
t
AA
t
OE
d
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STK14D88-25
MIN
MAX
25
25
25
12
3
3
10
0
10
0
25
STK14D88-35
MIN
MAX
35
35
35
15
3
3
13
0
13
0
35
STK14D88-45
MIN
MAX
45
45
45
20
3
3
15
0
15
0
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVQVd
t
GLQV
t
AXQX
t
ELQX
t
EHQZe
t
GLQX
t
GHQZ
e
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
b
t
ELICCHb
t
EHICCL
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low
Measured
±
200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlled
c,d,f
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
3
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E Controlled
c,f
ADDR ESS
t
E LE H
1
t
EL Q V
2
29
t
EHAX
11
t
EHI CC L
7
t
EHQ Z
E
27
6
t
ELQ X
G
t
AV QV
4
8
t
G L Q X
t
G L QV
9
t
GH Q Z
3
DQ (D ATA OUT)
10
t
ELI CC H
AC T IVE
DAT A VAL ID
I
CC
ST AND BY
Document Control #ML0033 Rev 2.0
Jan 2008
5
SIMTEK [ SIMTEK CORPORATION ]
