STK14EC16
SRAM WRITE CYCLE #3: LB, UB Controlled
g,h
t
AVAV
(15)
Preliminary
Address
E
t
AVBL
Address Valid
t
ELBH
(17)
(22)
t
BLBH
(18)
t
BHAX
(23)
LB , UB
t
AVBH
(21)
t
WLBH
(16)
W
t
DVBH
(19)
Data Input
Data Output
t
BHDX
(20)
Input Data Valid
High Impedance
AutoStore™/POWER-UP RECALL
SYMBOLS
NO.
Standard
26
27
28
29
t
HRECALL
t
STORE
V
SWITCH
V
CCRISE
t
HLHZ
Alternate
Power-up
RECALL
Duration
STORE
Cycle Duration
Low Voltage Trigger Level
V
CC
Rise Time
150
PARAMETER
MIN
MAX
20
12.5
2.65
ms
ms
V
μs
i
j
STK14EC16
UNITS
NOTES
Note i:
Note j:
t
HRECALL
starts from the time V
CC
rises above V
SWITCH
If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
AutoStore™/POWER-UP RECALL
V
CC
V
SWITCH
(28)
t
VCCRISE
(29)
AutoStore
POWER-UP
RECALL
Read & Write
Inhibited
**
t
STORE
(27)
**
t
STORE
(27)
t
HRECALL
(26)
t
HRECALL
(26)
POWER-UP
BROWN OUT
POWER-UP Read & Write
POWER DOWN
Read & Write
AutoStore
RECALL
RECALL
AutoStore
** AutoStore occures only if at least one SRAM Write has happened
Note: Read and Write cycles will be ignored during STORE, RECALL and while V
CC
is below V
SWITCH
Document Control #ML0061 Rev 1.1
Jan, 2008
8
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
