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STK14EX8-TF25I 参数 Datasheet PDF下载

STK14EX8-TF25I图片预览
型号: STK14EX8-TF25I
PDF下载: 下载PDF文件 查看货源
内容描述: 512Kx8自动存储的nvSRAM [512Kx8 Autostore nvSRAM]
分类和应用: 存储静态存储器
文件页数/大小: 18 页 / 203 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK14EC8
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are per-
formed regardless of whether a WRITE operation
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
Preliminary
READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into
the nonvolatile elements. Once a STORE cycle is
initiated, further memory inputs and outputs are dis-
abled until the cycle is completed.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address
2 Read Address
3 Read Address
4 Read Address
5 Read Address
6 Read Address
0x4E38
0x83E0
0x703F
Valid READ
Valid READ
Valid READ
HARDWARE STORE (HSB) OPERATION
The STK14EC8 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14EC8 will conditionally initiate a STORE oper-
ation after t
DELAY
. An actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin also
acts as an open drain driver that is internally driven
low to indicate a busy condition while the STORE
(initiated by any means) is in progress. This pin
should be externally pulled up if it is used to drive
other inputs.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14CA8 will
continue to allow SRAM operations for t
DELAY
. Dur-
ing t
DELAY
, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, t
DELAY
, to com-
plete. However, any SRAM WRITE cycles requested
after HSB goes low will be inhibited until HSB
returns high.
If HSB is not used, it should be left unconnected.
0xB1C7 Valid READ
0x7C1F Valid READ
0x8FC0 Initiate STORE Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence and that G is active. After the t
STORE
cycle
time has been fulfilled, the SRAM will again be acti-
vated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled or G con-
trolled READ operations must be performed:
1 Read Address
2 Read Address
3 Read Address
4 Read Address
5 Read Address
6 Read Address
0x4E38
0x83E0
0x703F
0x4C63
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
0xB1C7 Valid READ
0x7C1F Valid READ
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V
CC
<V
SWITCH
), an internal RECALL request will be
latched. When V
CC
once again exceeds the sense
voltage of V
SWITCH
, a RECALL cycle will automati-
cally be initiated and will take t
HRECALL
to complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK14EC8 software STORE cycle is initiated
by executing sequential E controlled or G controlled
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the t
RECALL
cycle time, the SRAM will once
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements. Care must be taken
so the controlling falling edge is glitch and ring free
so as not to double clock the read address.
Document Control #ML0060 Rev 1.0
April, 2007
12
Simtek Confidential