Preliminary
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
1
2
3
4
5
6
7
8
9
10
11
t
AXQXd
t
AVAVc
t
AVQVd
#2
t
ELQV
t
AVAVc
t
AVQVd
t
GLQV
t
AXQXd
t
ELQX
t
EHQZe
t
GLQX
t
GHQZe
t
ELICCHb
t
EHICCLb
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
15
0
7
0
25
3
3
7
0
10
15
15
10
3
3
10
PARAMETER
MIN
MAX
15
25
25
12
MIN
MAX
25
STK14EC8-15
STK14EC8-25
STK14EC8
STK14EC8-45
UNITS
MIN
MAX
45
45
45
20
3
3
15
0
15
0
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low
Measured
±
200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlled
c,d,f
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
3
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E Controlled
c,f
2
t
AVAV
ADDRESS
6
t
ELQX
1
t
ELQV
11
t
EHICCL
7
t
EHQZ
E
G
4
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
DATA VALID
t
GLQV
9
t
GHQZ
I
CC
STANDBY
Document Control #ML0060 Rev 1.0
April, 2007
5
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
