STK14EC8
NC
NC
A
0
A
1
A
2
A
3
A
4
E
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
W
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(TOP)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
NC
A
18
A
17
A
16
A
15
G
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
Preliminary
1
NC
NC
DQ
0
V
SS
V
CC
DQ
3
NC
A
18
2
G
NC
NC
DQ
1
3
A
0
A
3
A
5
A
17
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
E
NC
DQ
5
DQ
6
NC
W
A
11
6
NC
NC
DQ
4
V
CC
V
SS
DQ
7
NC
NC
A
B
C
D
E
F
G
H
DQ
2
V
CAP
NC
HSB
A
8
A
14
A
12
A
9
(TOP)
48-Ball FBGA
(See mechanical drawing on page 18)
44-Pin TSOP-II
(See mechanical drawing on page 17)
PIN DESCRIPTIONS
Pin Name
A
18
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
HSB
Input
I/O
Input
Input
Input
Power Supply
I/O
I/O
Description
Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable Input, Active Low: When selected low, enables data on the IO pins to be written to the address
location latched by the falling edge of CE.
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high
causes the DQ pins to tri-state.
Power: 3.0V, +20%, -10%
Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while
busy). When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resis-
tor keeps this pin high if not connected. (Connection Optional).
Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvol-
atile storage elements.
Ground
This pin is not connected to the die. (Do not connect in design; reserved for future use)
V
CAP
V
SS
NC
Power Supply
Power Supply
No Connect
Document Control #ML0060 Rev 1.1
Jan, 2008
2
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
