STK15C88
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
28 Pin 300 mil SOIC
28 Pin 330 mil SOIC
PIN NAMES
Pin Name
A
14
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
V
SS
Input
I/O
Input
Input
Input
Power Supply
Power Supply
I/O
Description
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, ±10%
Ground
Document Control #ML0016 Rev 0.3
February, 2007
2
SIMTEK [ SIMTEK CORPORATION ]
