STK15C68
8K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Deisgns
FEATURES
• Nonvolatile Storage without Battery Problems
• Directly Replaces 8K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
•
STORE
to Nonvolatile Elements Initiated by
Software or
AutoStore™
on Power Down
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention over Full Industrial
Temperature Range
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin 600 or 300 mil PDIP and 350 mil SOIC
Packages
DESCRIPTION
The STK15C68 is a fast
SRAM
with a nonvolatile ele-
ment incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
Nonvolatile Elements. Data transfers from the
SRAM
to
the Nonvolatile Elements (the
STORE
operation) can
take place automatically on power down using charge
stored in system capacitance. Transfers from the Non-
volatile Elements to the
SRAM
(the
RECALL
operation)
take place automatically on restoration of power. Initia-
tion of
STORE
and
RECALL
cycles can also be con-
trolled by entering control sequences on the
SRAM
inputs. The STK15C68 is pin-compatible with 8k x 8
SRAM
s and battery-backed
SRAM
s, allowing direct
substitution while enhancing performance. A similar
device (STK16C68) with an internally integrated
capacitor is available for systems with very fast slew
rates. The STK12C68, which uses an external capaci-
tor, is an alternative for these applications.
BLOCK DIAGRAM
QUANTUM TRAP
128 x 512
V
CC
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
ROW DECODER
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
128 x 512
RECALL
POWER
CONTROL
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
12
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 600 PDIP
28 - 350 SOIC
PIN NAMES
A
0
- A
12
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
DQ
0
- DQ
7
G
E
W
E
G
V
CC
V
SS
March 2006
1
Document Control # ML0009 rev 0.2