STK17T88
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
t
AXQX
d
t
AVAVc
t
AVQVd
SYMBOLS
#1
#2
t
ELQV
t
ELEHe
t
AVQVf
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
t
GLQX
t
GHQZe
t
ELICCLc
t
EHICCHc
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
45
3
3
10
0
15
25
25
12
3
3
15
STK17T88-25
MIN
MAX
25
45
45
20
STK17T88-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note c: W must be high during SRAM READ cycles.
Note d: Device is continuously selected with E and G both low
Note e: Measured
±
200mV from steady state output voltage.
Note f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlled
c,d,f
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
3
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E and G Controlled
a,f
ADDR ESS
t
E LE H
1
t
EL Q V
2
t
EHAX
11
t
EHI CC L
7
t
EHQ Z
29
E
27
t
ELQ X
6
G
t
AV QV
4
9
t
GH Q Z
3
t
G L Q X
DQ (D ATA OUT)
t
ELI CC H
AC T IVE
DAT A VAL ID
8
t
G L QV
10
I
CC
ST AND BY
Document Control #ML0024 Rev 2.0
Jan, 2008
6
SIMTEK [ SIMTEK CORPORATION ]
