STK17T88
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ ,
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
3
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
3
MAX
MIN
45
30
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK17T88-25
STK17T88-45
UNITS
note
g: If W is low when E goes low, the outputs remain in the high-impedance state.
note h: E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W Controlled
g,h
t
AVAV
ADDRESS
t
ELWH
E
17
14
19
12
t
WHAX
t
AVWH
t
AVWL
W
18
t
WLWH
t
DVWH
15
13
t
WHDX
16
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
20
DATA VALID
HIGH IMPEDANCE
t
WHQX
21
SRAM WRITE CYCLE #2:
E Controlled
g,h
t
AVAV
ADDRESS
t
AVEL
E
18
14
19
12
t
ELEH
t
EHAX
t
AVEH
W
t
WLEH
15
16
13
17
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
t
EHDX
Document Control #ML0024 Rev 2.0
Jan, 2008
7
SIMTEK [ SIMTEK CORPORATION ]
