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STK22C48-W45 参数 Datasheet PDF下载

STK22C48-W45图片预览
型号: STK22C48-W45
PDF下载: 下载PDF文件 查看货源
内容描述: 2K ×8 AutoStore⑩的nvSRAM QuantumTrap⑩ CMOS非易失性静态RAM [2K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 313 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK25C48
2K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
• Nonvolatile Storage without Battery Problems
• Directly Replaces 2K x 8 Static RAM, Battery-
Backed RAM or EEPROMs
• 25ns, 35ns and 45ns Access Times
STORE
to Nonvolatile Elements Initiated by
AutoStore™
on Power Down
RECALL
to SRAM Initiated by Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 24-Pin 600 PDIP Package
DESCRIPTION
The STK25C48 is a fast
SRAM
with a nonvolatile element
incorporated in each static memory cell. The
SRAM
can
be read and written an unlimited number of times, while
independent nonvolatile data resides in the
Nonvolatile
Elements
. Data transfers from the
SRAM
to the
Nonvola-
tile Elements
(the
STORE
operation) can take place auto-
matically on power down using charge stored in system
capacitance. Transfers from the
Nonvolatile Elements
to
the
SRAM
(the
RECALL
operation) take place automati-
cally on restoration of power. The nv
SRAM
can be used in
place of existing 2K x 8
SRAM
s and also matches the
pinout of 2K x 8 battery-backed
SRAM
s,
EPROM
s and
EEPROM
s, allowing direct substitution while enhancing
performance. No support circuitry is required for micro-
processor interfacing.
BLOCK DIAGRAM
QUANTUM TRAP
32 x 512
ROW DECODER
V
CC
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
1
2
24
23
22
21
20
19
18
17
16
15
14
13
A
5
A
6
A
7
A
8
A
9
STORE
STATIC RAM
ARRAY
32 x 512
RECALL
POWER
CONTROL
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
3
4
5
6
7
8
9
10
11
12
V
CC
A
8
A
9
W
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
24 - 600 PDIP
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
PIN NAMES
A
0
- A
10
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
DQ
0
- DQ
7
G
E
W
E
G
V
CC
V
SS
March 2006
1
Document Control # ML0005 rev 0.2