STK22C48
HARDWARE PROTECT
The STK22C48 offers hardware protection against
inadvertent
STORE
operation and
SRAM WRITE
s dur-
ing low-voltage conditions. When V
CAP
< V
SWITCH
, all
externally initiated
STORE
operations and
SRAM
WRITE
s are inhibited.
AutoStore can be completely disabled by tying V
CCX
to ground and applying + 5V to V
CAP
. This is the
AutoStore
Inhibit mode; in this mode
STORE
s are only
initiated by explicit request using the HSB pin.
shows the relationship between I
CC
and
READ
cycle
time. Worst-case current consumption is shown for
both
CMOS
and
TTL
input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on chip
enable). Figure 6 shows the same relationship for
WRITE
cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK22C48 depends on the following items: 1)
CMOS
vs.
TTL
input levels; 2) the duty cycle of chip
enable; 3) the overall cycle rate for accesses; 4) the
ratio of
READ
s to
WRITE
s; 5) the operating tempera-
ture; 6) the V
cc
level; and 7) I/O loading.
LOW AVERAGE ACTIVE POWER
The STK22C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
100
100
Average Active Current (mA)
Average Active Current (mA)
80
80
60
60
TTL
CMOS
20
40
TTL
20
CMOS
0
50
100
150
Cycle Time (ns)
200
40
0
50
100
150
Cycle Time (ns)
200
Figure 5: Icc (max) Reads
Figure 6: I
cc
(max) Writes
Document Control #ML0004 Rev 0.3
February 2007
10
SIMTEK [ SIMTEK CORPORATION ]
