U635H64
Write Cycle #1: W-controlled
j
t
cW
(12)
Ai
E
t
su(A-WH)
Address Valid
t
su(E)
(17)
t
h(A)
(21)
(16)
W
DQi
Input
t
su(A)
(15)
t
w(W)
(13)
t
su(D)
(19)
t
h(D)
(20)
Input Data Valid
t
dis(W)
(22)
t
en(W)
(23)
High Impedance
DQi
Output
Previous Data
Write Cycle #2: E-controlled
j
t
cW
(12)
Ai
t
su(A)
(15)
Address Valid
t
w(E)
(18)
t
h(A)
(21)
E
W
DQi
Input
t
su(W)
(14)
t
su(D)
(19)
t
h(D)
(20)
Input Data Valid
High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i:
j:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
E or W must be V
IH
during address transition.
STK Control #ML0052
6
Rev 1.0
March 31, 2006