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U63764DC70 参数 Datasheet PDF下载

U63764DC70图片预览
型号: U63764DC70
PDF下载: 下载PDF文件 查看货源
内容描述: CapStore 8K ×8的nvSRAM [CapStore 8K x 8 nvSRAM]
分类和应用: 静态存储器
文件页数/大小: 14 页 / 136 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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Obsolete - Not Recommended for New Designs
U63764
CapStore
8K x 8 nvSRAM
Features
Description
The U63764 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In non-volatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U63764 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an integra-
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U63764 combines the ease of use
of an SRAM with nonvolatile data
integrity.
Pin Description
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63764 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
CMOS non- volatile static RAM
8192 x 8 bits
70 ns Access Time
35 ns Output Enable Access Time
I
CC
= 15 mA at 200 ns Cycle Time
Unlimited Read and Write Cycles
to SRAM
Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
Software initiated STORE
Automatic STORE Timing
10
5
STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Single 5 V
±
10 % Operation
Operating temperature range:
0 to 70
°C
-40 to 85
°C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
RoHS compliance and Pb- free
Package: PDIP28 (600 mil)
Pin Configuration
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
PDIP
21
20
19
18
17
16
15
Top View
March 31, 2006
STK Control #ML0055
1
Rev 1.0