Receivers
The receivers convert EIA/TIA-232 levels to
TTL or CMOS logic output levels. The
SP3222EB receivers have an inverting tri-state
output. These receiver outputs (RxOUT) are tri-
stated when the enable control EN = HIGH. In
the shutdown mode, the receivers can be active
or inactive. EN has no effect on TxOUT. The
truth table logic of the
SP3222EB
driver and
receiver outputs can be found in
Table 2.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, a 5kΩ pulldown resistor to ground
will commit the output of the receiver to a HIGH
state.
Charge Pump
The charge pump is a
Sipex–patented
design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 5.5V power supplies. The
internal power supply consists of a regulated
dual charge pump that provides output voltages
5.5V regardless of the input voltage (V
CC
) over
the +3.0V to +5.5V range.
In most circumstances, decoupling the power
supply can be achieved adequately using a 0.1µF
bypass capacitor at C5 (refer to
Figures 8
and
9).
SHDN
0
0
1
1
EN
0
1
0
1
TxOUT
Tri-state
Tri-state
Active
Active
RxOUT
Active
Tri-state
Active
Tri-state
In applications that are sensitive to power-sup-
ply noise, decouple V
CC
to ground with a capaci-
tor of the same value as charge-pump capacitor
C1. Physically connect bypass capacitors as
close to the IC as possible.
The charge pumps operate in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pumps are enabled. If the output voltage
exceed a magnitude of 5.5V, the charge pumps
are disabled. This oscillator controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V
SS
charge storage — During this phase of
the clock cycle, the positive side of capacitors
C
1
and C
2
are initially charged to V
CC
. C
l+
is
then switched to GND and the charge in C
1–
is
transferred to C
2–
. Since C
2+
is connected to
V
CC
, the voltage potential across capacitor C
2
is now 2 times V
CC
.
Phase 2
— V
SS
transfer — Phase two of the clock con-
nects the negative terminal of C
2
to the V
SS
storage capacitor and the positive terminal of C
2
to GND. This transfers a negative generated
voltage to C
3
. This generated voltage is regu-
lated to a minimum voltage of -5.5V. Simulta-
neous with the transfer of the voltage to C
3
, the
positive side of capacitor C
1
is switched to V
CC
and the negative side is connected to GND.
Phase 3
— V
DD
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
1
produces –V
CC
in the negative
terminal of C
1
, which is applied to the negative
side of capacitor C
2
. Since C
2+
is at V
CC
, the
voltage potential across C
2
is 2 times V
CC
.
Phase 4
— V
DD
transfer — The fourth phase of the clock
connects the negative terminal of C
2
to GND,
and transfers this positive generated voltage
across C
2
to C
4
, the V
DD
storage capacitor.
© Copyright 2003 Sipex Corporation
Table 2. SP3222EB Truth Table Logic for Shutdown
and Enable Control
Rev. A Date:12/11/03
SP3222EB/3232EB True +3.0 to +5.5V RS-232 Transceivers
10
SIPEX [ SIPEX CORPORATION ]
