CHARGE PUMP
The charge pump is a
Sipex–patented
design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 10V power supplies. There
is a free–running oscillator that controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V
SS
charge storage —During this phase of
the clock cycle, the positive side of capacitors
C
1
and C
2
are initially charged to +5V. C
l+
is
then switched to ground and the charge in C
1–
is
transferred to C
2–
. Since C
2+
is connected to
+5V, the voltage potential across capacitor C
2
is
now 10V.
Phase 2
— V
SS
transfer — Phase two of the clock con-
nects the negative terminal of C
2
to the V
SS
storage capacitor and the positive terminal of C
2
to ground, and transfers the generated –l0V to
C
3
. Simultaneously, the positive side of capaci-
tor C
1
is switched to +5V and the negative side
is connected to ground.
Phase 3
— V
DD
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
1
produces –5V in the negative
terminal of C
1
, which is applied to the negative
side of capacitor C
2
. Since C
2+
is at +5V, the
voltage potential across C
2
is l0V.
Phase 4
— V
DD
transfer — The fourth phase of the clock
connects the negative terminal of C
2
to ground,
and transfers the generated l0V across C
2
to C
4
,
the V
DD
storage capacitor. Again, simultaneously
with this, the positive side of capacitor C
1
is
switched to +5V and the negative side is con-
nected to ground, and the cycle begins again.
Since both V
+
and V
–
are separately generated
from V
CC
; in a no–load condition V
+
and V
–
will
be symmetrical. Older charge pump approaches
that generate V
–
from V
+
will show a decrease in
the magnitude of V
–
compared to V
+
due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
V
CC
= +5V
+5V
C
1
+
–
C
4
+
–
+
C
2
+
–
–
V
DD
Storage Capacitor
V
SS
Storage Capacitor
–5V
–5V
C
3
Figure 1. Charge Pump — Phase 1
V
CC
= +5V
C
4
+
–
+
C
1
+
–
C
2
+
–
–
V
DD
Storage Capacitor
V
SS
Storage Capacitor
–10V
C
3
Figure 2. Charge Pump — Phase 2
+10V
a) C
2+
GND
GND
b) C
2–
–10V
Figure 3. Charge Pump Waveforms
Rev. 10/22/01
SP385E Enhanced +3V to +5V RS-232 Line Driver/Receiver
© Copyright 2001 Sipex Corporation
6
SIPEX [ SIPEX CORPORATION ]
