OPERATION
Over Current Protection
Over current protection on the SP6123 is imple-
mented through detection of an excess voltage
condition across the high side NMOS switch dur-
ing conduction. This is typically referred to as high
side R
DS(ON)
detection and eliminates the need of
an external sense resistor. The over current com-
parator charges an internal sampling capacitor
each time V(V
CC
)-V(SWN) exceeds the 200mV
(typ) internal threshold and the GH voltage is high.
The discharge/charge current ratio on the sam-
pling capacitor is about 2%. Therefore, provided
that the over current condition persists, the capaci-
tor voltage will be pumped up during each time GH
switches high. This voltage will trigger an over
current condition upon reaching a CMOS inverter
threshold. There are many advantages to this
approach. First, the filtering action of the gated
scheme protects against false and undesirable trig-
gering that could occur during a minor transient
overload condition or supply line noise. Further-
more, the total amount of time to trigger the fault
depends on the on-time of the high side NMOS
switch. Fifteen, 1µs pulses are equivalent to thirty,
500ns pulses or one, 15µs pulse, however, depend-
ing on the period, each scenario takes a different
amount of total time to trigger a fault. Therefore,
the fault becomes an indicator of average power in
the high side switch. The 200mV overcurrent
threshold has a 3400 ppm/°C temperature coeffi-
cients in an effort to first order match the thermal
characteristics of the R
DS(ON)
of the high side
NMOS switch. It assumed that the SP6123 will be
used in compact designs where there is a high
amount of thermal coupling between the high side
switch and the controller.
Output Drivers
The SP6123, unlike some other bipolar control-
ler IC’s, incorporates gate drivers with rail-to-
rail swing that help prevent spurious turn on due
to capacitive coupling. The driver stage consists
of one high side NMOS, 4Ω driver, GH, and one
low side, 4
Ω,
NMOS driver, GL, optimized for
driving external power MOSFET’s in a syn-
chronous buck topology. The output drivers
also provide gate drive non-overlap mechanism
that provides a dead time between GH and GL
transitions to avoid potential shoot-through prob-
Date: 5/25/04
lems in the external MOSFETs.
The following figure shows typical waveforms
for the output drivers.
As with all synchronous designs, care must be
taken to ensure that the MOSFETs are properly
chosen for non-overlap time, enhancement gate
drive voltage, “on” resistance R
DS(ON)
, reverse
transfer capacitance Crss, input voltage and
maximum output current.
GATE DRIVER TEST CONDITIONS
5V
90 %
FALL TIME
2V
90 %
2V
RISE TIME
10 %
GH(GL)
10 %
5V
GL(GH)
NON-OVERLAP
V(BST)
GH
Voltage
0V
V(VCC)
GL
Voltage
0V
V(VCC=VIN)
SWN
Voltage
~0V
- V(Diode) V
~ 2*V(VIN)
BST
Voltage
~ V(VIN)
TIME
SP6123 Low Voltage, Synchronous Step Down PWM Controller
© Copyright 2004 Sipex Corporation
8
SIPEX [ SIPEX CORPORATION ]
