OPERATION: Continued
regulation. Once RESET occurs T
ON
minimum
is reset, and the T
OFF
one-shot is triggered to
blank the loop comparator from starting a new
charge cycle for a minimum period. This blank-
ing period occurs during the noisy LX transition
to discharge, where spurious comparator states
may occur. For T
OFF
> T
BLANK
the loop is in a
discharge or wait state until the loop comparator
starts the next charge cycle by DRVON going
high.
If an over current occurs during charge the loop
is interrupted and DRVON is RESET. The off-
time one-shot pulse width is widened to T
OFF
=
K
OFF
/ V
OUT
, which holds the loop in discharge
for that time. At the end of the off-time the loop
is released and controlled by VOLOW. In this
manner maximum inductor current is controlled
on a cycle-by-cycle basis. An assertion of UVLO
(undervoltage lockout) or TSD (thermal shut-
down) holds the loop in no-charge until the fault
has ended.
On-Time Control - Discharge Phase
L = Inductor value
I
OUT
= Load current
R
CH
= PMOS on resistance, 0.3Ω typ.
If the I
OUT
* R
CH
term is negligible compared
with (V
IN
- V
OUT
), the above equation simplifies
to:
I
LR
≈
K
ON
L
For most applications, the inductor current ripple
controlled by the SP6654 is constant regardless
of input and output voltage. Because the output
voltage ripple is equal to:
V
OUT
(ripple) = I
LR
* R
ESR
where:
R
ESR
= ESR of the output capacitor
the output ripple of the SP6654 regulator is
independent of the input and output voltages.
For battery powered applications, where the
battery voltage changes significantly, the SP6654
provides constant output voltage ripple through-
out the battery lifetime. This greatly simplifies
the LC filter design.
The maximum loop frequency in CCM is de-
fined by the equation:
F
LP
≈
(V
IN
- V
OUT
) * (V
OUT
+ I
OUT
* R
DC
)
K
ON
* [V
IN
+ I
OUT
* (R
DC
- R
CH
)]
The discharge phase follows with the high side
PMOS switch opening and the low side NMOS
switch closing to provide a discharge path for
the inductor current. The decreasing inductor
current and the load current cause the output
voltage to drop. Under normal load conditions
when the inductor current is below the pro-
grammed limit, the off-time will continue until
the output voltage falls below the regulation
threshold, which initiates a new charge cycle via
the loop comparator.
The inductor current “floats” in continuous con-
duction mode. During this mode the inductor
peak current is below the programmed limit and
the valley current is above zero. This is to satisfy
load currents that are greater than half the mini-
mum current ripple. The current ripple, I
LR
, is
defined by the equation:
I
LR
≈
K
ON
L
*
V
IN
- V
OUT
- I
OUT
* R
CH
V
IN
- V
OUT
where:
F
LP
= CCM loop frequency
R
DC
= NMOS on resistance, 0.3Ω typ.
Ignoring conduction losses simplifies the loop
frequency to:
F
LP
≈
1
K
ON
*
V
OUT
V
IN
* (V
IN
- V
OUT
)
where:
AND’ing the loop comparator and the on-timer
reduces the switching frequency for load cur-
rents below half the inductor ripple current. This
increases light load efficiency. The minimum
on-time insures that the inductor current ripple
is a minimum of K
ON
/L, more than the load
Date: 2/1/05
SP6654 High Efficiency 800mA Synchronous Buck Regulator
© Copyright 2005 Sipex Corporation
9
SIPEX [ SIPEX CORPORATION ]
