PINOUT
V
OUT
V
CC
GND
PFI
1
8
V
BATTERY
RESET / RESET*
WDI
PFO
2 SP690T/S/R 7
SP802T/S/R
3 SP804T/S/R 6
SP805T/S/R
4
5
*
SP804T/S/R and SP805T/S/R only
PIN ASSIGNMENTS
Pin 1 —V
OUT
— Output Supply Voltage for
CMOS RAM. When V
CC
is above the
reset threshold, V
OUT
connects to V
CC
through a P-channel MOSFET switch.
When V
CC
falls below the V
SW
and
V
BATTERY
, V
BATTERY
connects to V
OUT
.
Connect to V
CC
if no battery is used.
Pin 2 — V
CC
— +5V Supply Input
Pin 3 — GND — Ground reference for all
signals
Pin 4 — PFI — Power-Fail Comparator Input.
When PFI is less than 1.25V or when V
CC
falls below the V
SW
, PFO goes LOW,
otherwise PFO remains HIGH. Connect
to GND if unused.
Pin 5
— PFO — Power-Fail Comparator
Output. Leave open if unused.
Pin 7 for
SP690_/802_ only
— Active-LOW
Reset Output. — Whenever RESET is
triggered by a watchdog timeout, it goes
LOW for 200ms. It stays LOW whenever
V
CC
is below the reset threshold and re-
mains LOW for 200ms after V
CC
rises
above the reset threshold or when the
watchdog triggers a reset.
Pin 7 for
SP804_/805_ only
— Active-HIGH
Open-Drain Reset Output. — The
inverse operation of RESET.
Pin 8 — V
BATTERY
— Backup-Battery Input.
When V
CC
falls below V
SW
and V
BATTERY
,
V
OUT
switchesfrom V
CC
to V
BATTERY
.
When V
CC
rises above the reset threshold,
V
OUT
reconnects to V
CC
. V
BATTERY
may
exceed V
CC
. Connect to V
CC
if no battery
is used.
Pin 6 — WDI — Watchdog Input. If WDI
remains HIGH or LOW for 1.6 seconds,
the internal watchdog timer triggers a
reset. The internal watchdog timer clears
when reset is asserted or WDI sees a
rising or falling edge.
The watchdog
function cannot be disabled.
SP690T/S/R DS/10
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
6
SIPEX [ SIPEX CORPORATION ]
