SP7650
Evaluation Board Manual
Easy Evaluation for the
SP7650ER 12V Input, 0 to 3A
Output Synchronous Buck
Converter
Built in Low Rds(on) Power FETs
UVLO Detects Both VCC and VIN
High Integrated Design, Minimal
Components
High Efficiency: 90%
Feature Rich: UVIN, Programmable
Softstart, External VCC Supply and
Output Dead Short Circuit Shutdown
SP7650EB SCHEMATIC
U1
SP7650
1
PGND
PGND
PGND
GND
VFB
COMP
UVIN
GND
SS
VIN
VIN
VIN
VIN
LX
LX
LX
LX
VCC
GND
GND
GND
BST
NC
LX
LX
LX
26
25
24
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
L1
6.8uH
C3
22uF
6.3V
CVCC
2.2uF
RBST
20
DBST
SD101AWS
CBST
6,800pF
RZ3
7.15k,1%
CZ3
150pF
CZ2
RZ2
1,000pF 15k,1%
CP1
22pF
CF1
100pF
fs=300Khz
VOUT
3.30V
0-3A
R1
68.1k,1%
GND2
C3
CERAMIC
1210
X5R
R2
21.5k,1%
CSS
47nF
10
11
12
13
12V
VIN
C1
CERAMIC
1210
X5R
R3
200k,1%
C1
22uF
16V
R4
100k,1%
R6
464,5%
1210
C2
0.1uF
Notes:
D1
BZX384B5V6
Vz=5.6V
U1 Bottom-Side Layout should has
three Contacts which are
isolated from one of another, QT
& QB Drain Contact and
Controller GND Contact
All resistor & capacitor size
0603 unless other wise specify
GND
Date: 01/04/05
SP7650 Evaluation BoardManual
Copyright 2005 Sipex Corporation
SIPEX [ SIPEX CORPORATION ]
