PIN DESCRIPTION
Pin #
-3
4,8,19-21
Pin Name
P
gnD
GND
Description
Ground connection for the synchronous rectifier.
Ground Pin. The control circuitry of the IC and lower power driver are referenced
to this pin. Return separately from other ground traces to the (-) terminal of C
Out
.
Feedback Voltage and Short Circuit Detection pin. The inverting input of the Error
Amplifier and serves as the output voltage feedback point for the Buck Converter.
The output voltage is sensed and can be adjusted through an external resistor
divider. Whenever VFB drops 0.25V below the positive reference, a short circuit
fault is detected and the IC enters hiccup mode.
Output of the Error Amplifier. Internally connected to the inverting input of the
PWM comparator. An optimal filter combination is chosen and connected to this
pin and either ground or VFB to stabilize the voltage mode loop.
UVLO input for V
in
voltage. Connect a resistor divider between V
in
and UV
in
to
set minimum operating voltage.
Soft Start. Connect an external capacitor between SS and GND to set the soft
start rate based on the 0µA source current. The SS pin is held low via a mA
(min.) current during all fault conditions.
Input connection to the high-side N-channel MOSFET. Place a decoupling capaci-
tor between this pin and PGND.
Connect an inductor between this pin and V
Out
.
No Connect.
High-side driver supply pin. Connect BST to the external boost diode and capaci-
tor as shown in the Typical Application Circuit on page one. High-side driver is
connected between BST and SWN pin.
Input for external 5V bias supply.
5
V
fb
6
7
9
0-3
4-6,23-
26
7
8
22
COMP
UVIN
SS
V
in
LX
NC
BST
V
cc
General Overview
The SP7652 is a fixed frequency, voltage
mode, synchronous PWM regulator opti-
mized for high efficiency. The part has been
designed to be especially attractive for split
plane applications utilizing 5V to power
the controller and 3V to 20V for step down
conversion.
The heart of the SP7652 is a wide bandwidth
transconductance amplifier designed to ac-
commodate Type II and Type III compensa-
tion schemes. A precision 0.8V reference,
present on the positive terminal of the error
amplifier, permits the programming of the
output voltage down to 0.8V via the V
fb
pin.
The output of the error amplifier,
COMP,
which is compared to a .V peak-to-peak
ramp, is responsible for trailing edge PWM
control. This voltage ramp and PWM control
logic are governed by the internal oscillator
that accurately sets the PWM frequency to
600kHz.
Rev F: /0/06
THEORY OF OPERATION
The SP7652 contains two unique control
features that are very powerful in distributed
applications. First, asynchronous driver con-
trol is enabled during start up, to prohibit the
low side NFET from pulling down the output
until the high side NFET has attempted to
turn on. Second, a 100% duty cycle timeout
ensures that the low side NFET is periodically
enhanced during extended periods at
100%
duty cycle. This guarantees the synchronized
refreshing of the BST capacitor during very
large duty cycle ratios.
The SP7652 also contains a number of
valuable protection features. Programmable
UVLO allows the user to set the exact V
in
value at which the conversion voltage can
safely begin down conversion, and an inter-
nal V
cc
UVLO ensures that the controller
itself has enough voltage to operate properly.
Other protection features include thermal
shutdown and short-circuit detection. In the
event that either a thermal, short-circuit, or
© Copyright 2006 Sipex Corporation
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
4
SIPEX [ SIPEX CORPORATION ]
