SDM-08060-B1F 869-894 MHz 65W Power Amp Module
Pin Description
Pin #
1
2,4,7,9
3
5
6
8
10
Flange
Function
V
GS1
Ground
RF Input
V
GS2
V
D2
RF Output
V
D1
Ground
Description
LDMOS FET Q1 gate bias. V
GSTH
3.0 to 5.0 VDC. See Notes 2, 3 and 4
Module Topside ground.
Internally DC blocked
LDMOS FET Q2 gate bias. V
GSTH
3.0 to 5.0 VDC. See Notes 2, 3 and 4
LDMOS FET Q2 drain bias. See Note 1.
Internally DC blocked
LDMOS FET Q1 drain bias. See Note 1.
Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures
optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for
Power Modules.
Simplified Device Schematic
1
2
3
4
5
Case Flange = Ground
Q2
10
Q1
9
8
7
6
Note 1:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the V
D
leads to
accommodate modulated signals.
Note 2:
Gate voltage must be applied to V
GS
leads
simultaneously with or after application of drain voltage to pre-
vent potentially destructive oscillations. Bias
voltages should never be applied to a module unless it is prop-
erly terminated on both input and output.
Note 3:
The required V
GS
corresponding to a specific I
DQ
will vary from
module to module and may differ between V
GS1
and V
GS2
on
the same module by as much as ±0.10 volts due to the normal
die-to-die variation in threshold voltage.
LDMOS transistors.
Note 4:
The threshold voltage (V
GSTH
) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature
Compensation.
Note 5:
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700° F, and the soldering iron
tip should not be in direct contact with the lead for longer than
10 seconds. Refer to app note AN054 (www.sirenza.com) for
further installation
instructions.
Absolute Maximum Ratings
Parameters
Drain Voltage (V
DD
)
RF Input Power
Load Impedance for Continuous Operation Without
Damage
Control (Gate) Voltage, VDD = 0 VDC
Output Device Channel Temperature
Operating Temperature Range
Storage Temperature Range
Value
35
+37
5:1
15
+200
-20 to
+90
-40 to
+100
Unit
V
dBm
VSWR
V
ºC
ºC
ºC
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-104208 Rev F
SIRENZA [ SIRENZA MICRODEVICES ]
