Product Description
Sirenza Microdevices’ SHF-0289 is a high performance AlGaAs/GaAs
Heterostructure FET (HFET) housed in a low-cost surface-mount plastic
package. The HFET technology improves breakdown voltage while minimizing
Schottky leakage current resulting in higher PAE and improved linearity.
Output power at 1dB compression for the SHF-0289 is +30dBm when
biased for Class AB operation at 7V,200mA. The +43 dBm third order
intercept makes it ideal for high dynamic range, high intercept point
requirements. It is well suited for use in both analog and digital wireless
communication infrastructure and subscriber equipment including 3G,
cellular, PCS, fixed wireless, and pager systems.
SHF-0289
SHF-0289Z
Pb
RoHS Compliant
&
Green
Package
0.05 - 6 GHz, 1.0 Watt
GaAs HFET
The matte tin finish on Sirenza’s lead-free package utilizes a post anneal-
ing process to mitigate tin whisker formation and is RoHS compliant per EU
Product Features
Directive 2002/95. This package is also manufactured with green molding
• Now available in Lead Free, RoHS
compounds that contain no antimony trioxide nor halogenated fire retar-
Compliant, & Green Packaging
dants.
Typical Gain Performance (7V,200mA)
40
35
30
25
20
15
10
5
0
0
1
2
Gain, Gmax (dB)
Gmax
Gain
• High Linearity Performance at 1.96 GHz
+30 dBm P1dB
+43 dBm OIP3
+23.7 dBm IS-95 Channel Power
+14.6 dB Gain
• +21.7 dBm W-CDMA Channel Power
• High Drain Efficiency (>50% at P1dB)
• See App Note AN-032 for circuit details
Applications
3
4
5
6
Frequency (GHz)
• Analog and Digital Wireless Systems
• 3G, Cellular, PCS
• Fixed Wireless, Pager Systems
( u n le s s o t h e r w is e n o t e d )
S ym bol
D e v ic e C h a r a c t e r is t ic s
T e s t C o n d it io n s , 2 5 C
V
D S
= 7 V , I
D Q
= 2 0 0 m A
Test
F re q u e n c y
0 .9 0 G H z
1 .9 6 G H z
2 .1 4 G H z
0 .9 0 G H z
1 .9 6 G H z
1 .9 6 G H z
1 .9 6 G H z
1 .9 6 G H z
1 .9 6 G H z
U n it s
dB
dB
dB
dB
dB m
dB m
dB m
dB m
dB
m A
m S
V
V
V
o
M in
-
-
-
1 6 .7
1 3 .1
4 0 .5
2 8 .7
-
-
408
288
- 3 .0
-
-
-
-
-
-
Typ
23
20
1 9 .5
1 8 .5
1 4 .6
4 3 .0
3 0 .2
2 3 .7
4 .0
588
396
- 1 .9
-1 7
-2 2
41
-
-
-
M ax
-
-
-
2 0 .3
1 6 .1
-
-
-
-
768
504
- 1 .0
-1 5
-1 7
-
8 .0
280
1 .4
Gm ax
S
M a x i m u m A v a i la b le G a i n
In s e r t i o n G a i n
P o w e r G a in
[2 ]
[1 ]
Z
S
= Z
S
*, Z
L
= Z
L
*
Z
S
= Z
L
= 5 0 O hm s
A p p li c a t i o n C i r c u i t
[2 ]
21
G a in
O IP 3
P 1dB
P
C HA N
O u t p u t T h i r d O r d e r In t e r c e p t P o i n t
O u tp u t 1 d B C o m p r e s s i o n P o i n t
[2 ]
A p p li c a t i o n C i r c u i t
A p p li c a t i o n C i r c u i t
A p p li c a t i o n C i r c u i t
A p p li c a t i o n C i r c u i t
V
V
D S
IS - 9 5 C h a n n e l P o w e r ( - 4 5 d B c A C P R )
N o is e F ig u re
[2 ]
NF
I
D S S
g
V
B V
B V
m
S a tu r a te d D r a i n C u r r e n t
T r a n c o n d u c ta n c e
P i n c h - O f f V o lt a g e
[1 ]
= V
= V
D SP
, V
, V
GS
= 0V
= - 0 .2 5 V
D S
D SP
GS
P
V
[1 ]
D S
= 2 . 0 V , I
D S
= 1 . 2 m A
GS
G a t e - S o u r c e B r e a k d o w n V o lt a g e
G a t e - D r a i n B r e a k d o w n V o lt a g e
T h e r m a l R e s i s ta n c e
O p e r a t i n g V o lt a g e
O p e r a ti n g C u r r e n t
P o w e r D i s s i p a ti o n
[3 ]
[1 ]
I
G S
= 2 . 4 m A , d r a i n o p e n
I
G D
= 2 . 4 m A , V
G S
G D
= - 5 .0 V
R th
V
D S
ju n c t i o n - t o - le a d
d ra in -s o u rc e
d ra in -s o u rc e , q u ie s c e n t
C /W
V
m A
C
I
D Q
P
D IS S
[3 ]
[3 ]
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board.
The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR.
[3] Maximum recommended power dissipation is specified to maintain T
J
<140C at T
L
=85C. V
DS
* I
DQ
< 1.4W is recommended for continuous reliable operation.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent
rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or
systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MM
http://www.sirenza.com
1
EDS-101241 Rev E
SIRENZA [ SIRENZA MICRODEVICES ]
