ST7920
Pin Description
Name
XRESET
PSB
No.
11
23
I/O
I
I
Connects to
―
―
Function
System reset input (low active).
Interface selection:
0: serial mode;
1: 8/4-bit parallel bus mode.
Parallel Mode:
Register select.
0: Select instruction register (write)
or busy flag, address counter (read);
1: Select data register (write/read).
Serial mode:
Chip select.
1: chip enabled;
0: chip disabled.
When chip is disabled, SID and SCLK
should be set as
“H”
or
“L”.
Transcient
of SID and SCLK is not allowed.
Parallel Mode:
Read/Write control.
0: Write;
1: Read.
Serial Mode:
Sserial data input.
Parallel Mode:
1: Enable trigger.
Serial Mode:
Serial clock.
Higher nibble data bus of 8-bit interface
and data bus for 4-bit interface
Lower nibble data bus of 8-bit interface.
Latch signal for extension segment
drivers.
Shift clock for extension segment
drivers.
AC signal for extension segment drivers
voltage inversion.
Data output for extension segment
drivers.
Common signals.
Segment signals.
RS(CS*)
17
I
MPU
RW(SID*)
18
I
MPU
E(SCLK*)
D4 to D7
D0 to D3
CL1
CL2
M
DOUT
COM1 to
COM32
SEG1 to
SEG64
V0 to V4
19
28~31
24~27
12
13
15
16
40~71
136~73
1~3,7,8
I
I/O
I/O
O
O
O
O
O
O
―
MPU
MPU
MPU
Extension segment drv.
Extension segment drv.
Extension segment drv.
Extension segment drv.
LCD
LCD
―
LCD bias voltage.
V0 ~ V4
≦
7V.
V
DD
10,14
I
Power
V
DD
: 2.7V to 5.5V.
Vss
9,20
I
Power
VSS: 0V.
Using internal oscillator:
5.0V R=33K;
OSC1,
Resistors
21,22
I, O
2.7V R=18K.
OSC2
Using external clock:
Use OSC1 as external clock input.
LCD voltage doubler output.
VOUT
33
O
Resistors
VOUT
≦
7V.
*Note: The OSC pin must have the shortest wiring pattern of all other pins. To prevent noise from other
signal lines, it should also be enclosed by the largest GND pattern. Poor anti-noise characteristics on the
OSC line will result in malfunction, or adversely affect the clock’s duty ratio.
V4.0
7/49
2008/08/18
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
