SL74HC573
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
Maximum Propagation Delay,Latch Enable
to Q (Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enabled
Output)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Guaranteed Limit
25
°C
to
-55°C
150
30
26
160
32
27
150
30
26
150
30
26
60
12
10
10
15
≤85°C
190
38
33
200
40
34
190
38
33
190
38
33
75
15
13
10
15
≤125°C
225
45
38
240
48
41
225
45
38
225
45
38
90
18
15
10
15
Unit
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZH
, t
PZL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
23
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
Minimum Hold Time, Latch
Enable to Input D
(Figure 4)
Minimum Pulse Width, Latch
Enable (Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
°C
to
-55°C
50
10
9
5
5
5
75
15
13
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
95
19
16
1000
500
400
≤125°C
75
15
13
5
5
5
110
22
19
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r,
t
f
ns
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
