SL74HC165
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The SL74HC165 is identical in pinout to the LS/ALS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the rising
edge of either Clock or Clock Inhibit (see the Function Table).
The 2
-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC165N Plastic
SL74HC165D SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Serial Shift/
Parallel Load
L
H
H
H
H
H
H
H
L
L
X
H
L
H
X
L
Clock
H
Clock
Inhibit
X
L
L
S
A
X
L
H
L
H
X
X
X
A-H
a...h
X
X
X
X
X
X
X
no change
No Clock
Internal Stages
Q
A
a
L
H
L
H
Q
B
-Q
G
b-g
Q
An
-Q
Fn
Q
An
-Q
Fn
Q
An
-Q
Fn
Q
An
-Q
Fn
no change
Output
Q
H
h
Q
Gn
Q
Gn
Q
Gn
Q
Gn
Serial Shift via Clock
Inhibit
Inhibited Clock
Asynchronous Parallel Load
Serial Shift via Clock
Operation
X = Don’t Care
Q
An
-Q
Fn
= Data shifted from the preceding stage
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
