SL74HC4094
8-Bit Serial-Input Shift Register With Latched
3-State Outputs
High-Performance Silicon-Gate CMOS
The SL74HC4094 is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the
shift register on the positive going transition of the clock input signal.
The output of the last stage SQ
H
can be used to cascade several
devices.
Data on the SQ
H
output is transferred to a second output (SQ
H
’) on
the following negative transition of the clock input signal. The data of
each stage of the shift register is provided with a latch, which latches
data on the negative going transition of the Strobe input signal. When
the Strobe input is held high, data propagates through the latch to a 3-
state output buffer.
This buffer is enabled when Output Enable input is taken high.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC4094N Plastic
SL74HC4094D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock Output
Enable
PIN 16 =V
CC
PIN 8 = GND
L
L
H
H
H
H
NC = No Change
Z = high impedance
X = don’t care
System Logic
Semiconductor
Parallel
Outputs
Strobe
X
X
L
H
H
X
A
X
X
Q
A
Z
Z
Q
N
Z
Z
NC
Q
N-1
Q
N-1
NC
Serial
Outputs
SQ
H
SQ
H
’
Q6
NC
NC SQ
H
Q6
Q6
Q6
NC
NC
NC
X NC
L
H
L
H
X NC
NC SQ
H
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
