SL74HC595
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
T
su
Parameter
Minimum Setup Time,Serial Data
Input A to Shift Clock (Figure 5)
Minimum Setup Time, Shift Clock to
Latch Clock (Figure 6)
Minimum Hold Time, Shift Clock to
Serial Data Input A (Figure 5)
Minimum Recovery Time, Reset
Inactive to Shift Clock (Figure 2)
Minimum Pulse Width, Reset (Figure
2)
Minimum Pulse Width, Shift Clock
(Figure 1)
Minimum Pulse Width, Latch Clock
(Figure 6)
Maximum Input Rise and Fall Times
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
50
10
9
75
15
13
5
5
5
50
10
9
60
12
10
50
10
9
50
10
9
1000
500
400
≤85°C
65
13
11
95
19
16
5
5
5
65
13
11
75
15
13
65
13
11
65
13
11
1000
500
400
≤125°C
75
15
13
110
22
19
5
5
5
75
15
13
90
18
15
75
15
13
75
15
13
1000
500
400
Unit
ns
T
su
ns
t
h
ns
T
rec
ns
T
w
ns
T
w
ns
T
w
ns
t
r
, t
f
ns
SLS
System Logic
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
