SL74HC109
Dual J -K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC109 is identical in pinout to the LS/ALS109. The device
inputs are compatible with standard CMOS outputs, with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs
with the next low-to-high transition of the clock. Both Q to Q outputs
are available from each flip-flop.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µ
A
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC109N Plastic
SL74HC109D SOIC
T
A
= -55
°
to 125
°
C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
H
Reset
H
L
L
H
H
H
H
H
L
Clock
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Outputs
Q
H
L
H
*
Q
L
H
H
*
L
H
Toggle
No Change
H
L
No Change
X = Don’t care
*
Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
SLS
System Logic
Semiconductor